For this type of complex condition processing system, Patent Document 1, discloses a configuration for parallel processing of a plurality of instructions. The configuration includes a flag register means, a logical product means, and an instruction fetch address selection means. The flag register means is able to set/reset bits independently in parallel in accordance with a true/false value of the result of execution of a plurality of instructions for comparison. The logical product means takes a bit-by-bit logical product of contents stored in the flag register means and a mask value specified by a conditional branch instruction. The instruction fetch address selection means selects, as an address of an instruction to be executed next, either an address of a branch target specified by the conditional branch instruction or an address of an instruction next following the conditional branch instruction, depending on whether or not the output value of the logical product means is zero. It is determined whether or not branching is to be executed with bit states of respective bit positions of the flag register means specified by the mask value as the complex condition.
In a parallel processing apparatus, described in Patent Document 1, there are provided a plurality of decoders for decoding compare instructions. These decoders execute a plurality of compare instructions simultaneously. The results are stored in a flag register, and conditional branching is performed in dependence upon the states of the flag register.
The complex conditional processing system, disclosed in Patent Document 1, is outlined. An assembler instruction (compiled result) corresponding to a program by the C language:
if (X>1 && X<10 && X!=5)
{processing when the complex condition is met}
where && denotes an AND operation, is taken as an example for explanation. It should be noticed that, with the above program of the C language, branching takes place in such a manner that, if all of the conditions X>1, X<10 and X!=5, are met, the next instruction, that is, the {processing when the complex condition is met}, is executed. If at least one or more of the three conditions is not met, the {processing when the complex condition is met} is not executed. According to Patent Document 1, the compiled result of the above program of the C language may be represented by
SLE X, 1, 0 SGE X, 10, 1 SEQ X, 5, 2
BNZ 7, $1
(processing when complex condition is met)
$1 (processing at the branch target)
In the first compare instruction SLE X, 1, 0, . . . , comparison operation of the complex condition is performed. The SLE compare instruction is a compare instruction of the format “SLE A, B, C” in which A and B are compared to each other and in which a bit C (any of bit 0 to bit 3) of the flag register is set to “1” if A<=B, while being set to “0” if otherwise. The SGE compare instruction is a compare instruction of the format “SGE A, B, C” in which A and B are compared to each other and in which a bit C (any of bit 0 to bit 3) of the flag register is set to “1” if A>=B, while being set to “0” if otherwise. A SQE compare instruction is a compare instruction of the format “SQE A, B, C” in which A and B are compared to each other and in which a bit C (any of bit 0 to bit 3) of the flag register is set to “1” if A=B, while being set to “0” if otherwise.
In the second conditional branch instruction BNZ 7, $1, bit operations on the results of the comparison operation of the complex condition and the branching condition value (mask value) “7” are performed bit by bit. If the conditions fail to hold, a jump to the address $1 occurs. The BNZ conditional branch instruction is of the format “BNZ M, L”. A logical product is taken between M (mask value) and the corresponding bits of the flag register. A zero decision circuit decides whether or not the results of logical product are all “0”. If the results are all zero, the zero decision circuit outputs “1”, while outputting “0” if otherwise. An output signal of the zero decision circuit (zero/non-zero decision result) is output as a signal indicating branch-taken/branch-not-taken. If branch is taken, the branch to an address specified by L occurs. In BNZ 7, $1, the mask value is “0111” and conditional branching takes place in accordance with the values of bits 0 to 2 of bits 0 to 3 of the flag register.
In this manner, two instructions, that is, compare instruction SLE X, 1, 0, . . . and conditional branch instruction BNZ, are used.
In this exemplary program, if at least one or more of the three compare conditions for a value X (corresponding to a register), that is, (X>1, X<10 and X!=5) fails to hold, that is, if at least one of three conditions: X<=1, X>=10 and X=5, in terms of an assembler code, holds, the branching to the branch target $1 occurs. The results of the comparison may be inverted to set all logical conditions to the OR condition.
In Patent Document 2, there is disclosed a configuration in which a condition value selector selects a value for selecting an external state signal and a value for code control, using an instruction output by a pipelining register. The so selected value is used to select a signal from the external state signal by a condition code selector, and a code controller decides the polarity and a next address selector is able to select and output a non-branch address or a branch address. Thus, in case of changing the condition for branching or the polarity decision condition of a program sequence, the condition for branching or the polarity decision condition can be changed simply by changing the contents of the condition register, without changing the instruction word stored in the instruction memory.
[Patent Document 1] JP Patent Kokai Publication No. JP-A-5-274143
[Patent Document 2] JP Patent Kokai Publication No. JP-A-6-290044
The entire disclosures of Patent Documents 1 and 2 are incorporated herein by reference thereto. The following analyses are given by the present inventor.
With the complex conditional processing scheme, described in Patent Document 1, no particular problem is raised in case the complex condition is executed only once. However, if the scheme is used for loop processing of repeatedly executing the same complex condition, there are problems described in the below. It is noted that the following is the results of analyses by the present inventor.
The first problem is that, since the two instructions, that is, the compare instruction of the complex condition and the conditional branch instruction, need to be executed as a set, a number of execution cycles corresponding to two steps is required for each conditional branch processing. This point will be discussed in detail hereinbelow.
With the complex conditional processing scheme disclosed in Patent Document 1, a number of cycles corresponding to two instructions are needed, as shown in FIGS. 11A and 11B. It should be noticed that FIGS. 11A and 11B are formulated by the present inventor to illustrate the operation of the complex conditional processing system disclosed in Patent Document 1.
In the example shown in FIGS. 11A and 11B, six cycles, corresponding to two instructions, namely the compare instruction (SLE X, 1, 0, . . . ) and the conditional branch instruction (BNZ), are needed for each conditional branch processing. These six cycles are F (instruction fetch), D (instruction decode), Ex (execute), F, D, Ex). See 8-1, 8-2 and 8-3 of FIG. 11. The compare instruction for the complex condition (SLE X, 1, 0, . . . ) executes respective comparison operations corresponding to a plurality of conditions making up the complex condition in parallel and set the results of the comparison operations in specified bits of the flag register. The conditional branch instruction (BNZ) decides on branching/non-branching based on the results of logical operations of the flag register value and the mask value. Thus, with the complex conditional processing scheme, disclosed in Patent Document 1, the instruction is divided into two, namely the compare instruction and the conditional branch instruction, so that at least two cycles, that is, a cycle for instruction fetch and a cycle for instruction decoding, need to be executed at least twice, resulting in an increased number of cycles. The number of cycles in the loop processing is increased appreciably, thus limiting the processing performance.
The second problem is that, in the complex conditional processing scheme, disclosed in Patent Document 1, the compare instruction is configured so that the plural condition making up the complex condition are evaluated with one instruction in parallel, as a result of which, a long instruction word is needed to represent a plurality of conditions.
For example, regarding the compare instruction:
SLE X, 1, 0 SGE X, 10, 1 SEQ X, 5, 2
8 bits are needed for an instruction code (operation code) for a processor assumed to have up to 256 instructions,
3 bits are needed for comparator selection, because there are six comparators and one out of six comparators is to be selected,
4 bits are needed for register selection, if one out of 16 registers is to be selected, as for an operand X,
4 bits are needed if one out of 0 to 15 may be specified as condition value of an operand (it should be noted that 1 of “SLE X, 1, 0” corresponds to 1 on the right side of the condition for comparison X<=1), and
In addition, 2 bits are needed for specifying the bit position in the flag register of an operand (any one of bits of 0 to 3).
Then, 8+4+(3+4+2)×3=39 bits are needed for the instruction (see Table 1 below).
TABLE 1Instruc-compar-conditionflagcompar-compar-flagcompar-conditionflagtion codeRegisterator 0value 0bit 1ator 1ator 1bit 2ator 2value 2bit 38 bit4 bit3 bit4 bit2 bit3 bit4 bit2 bit3 bit4 bit2 bitXLE10GE101EQ52XXXXXXXX011000100101101001000010110XXXX
The instruction word (byte) length is increased because the parallel processing apparatus of Patent Document 1 specifies all conditions constituting the complex condition with one instruction (compare instruction).